1. Field of the Invention
This invention relates to a magnetic random access memory (MRAM) that utilizes the magneto-resistive effect.
2. Description of the Related Art
Magnetic random access memories that utilize the tunneling magneto-resistive (TMR) effect are disclosed, interior, in Patent Documents 1 through 3 and Non-Patent Documents 1 through 5. Such magnetic random access memories are characterized in that they utilize the state of magnetization of MTJ (magnetic tunnel junction elements) for storing data.
A data is written into an MTJ element by flowing 2 write currents to mutually intersecting write word/bit lines at the MTJ element to generate a magnetic field that determines the state of magnetization of the MTJ element. Since a write bit line normally operates as read bit line, it is also referred to as write/read bit line.
The write/read bit line is connected to a sense amplifier and, for a read operation, it is electrically charged in order to read a data. However, because a driver/sinker or a switching element that is used for a write operation is connected to a write/read bit line, the write/read bit line is made to have a large load capacity, which is disadvantageous for a high speed read operation.
To realize a high speed read operation, it is necessary to use write/read bit lines having a small load capacity. For this reason, an arrangement where write bit lines and read bit lines are provided independently and only read bit lines are electrically charged for a read operation has been proposed recently. Such an arrangement is advantageous for high speed read operations because it is no longer necessary to take the load capacity attributable to the driver/sinker or the switching element connected to each write bit line into consideration.
Meanwhile, in a magnetic random access memory where a bit data is stored in a MTJ element (a cell), the use of a bias current/potential that is necessary for reading the cell data and a reference current/potential that operates as reference for determining the value of the cell data is required. Therefore, a bias current/potential generation circuit and a reference current/potential generation circuit need to be provided in a chip to give rise to a problem of a large chip area.
Thus, it will be advantageous if some of the memory cells of a memory cell array can be used as reference cells for generating a bias current/potential or reference current/potential so as to reduce the chip area, realize a high speed read operation and simplify the data storing operation.
The above-cited Patent Documents 1 through 3 and Non-Patent Documents 1 through 5 are listed below.    Patent Document 1: Jpn. Pat. Appln. KOKAI Publication No. 2002-170376    Patent Document 2: U.S. Pat. No. 6,545,906    Patent Document 3: U.S. Pat. No. 6,081,445    Non-Patent Document 1: M. Durlam et al. “A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects”, IEEE, 2002 Symposium on VLSI Circuits Digest of Technical Papers    Non-Patent Document 2: T. HONDA et al. “MRAM-Writing Circuitry to Compensate for Thermal-Variation of Magnetization-Reversal Current”, 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 156–157, July 2002    Non-Patent Document 3: Roy Scheuerlein et al. “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000 Technical Digest, pp. 128–129    Non-Patent Document 4: A Bette et al. “A High-Speed 128 Kbit MRAM Core for Future Universal Memory Applications”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 217–220, July 2003    Non-Patent Document 5: A. R. Sitaram et al. “A 0.18 μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 15–16, July 2003.